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4 Mbit (512K x8) SuperFlash EEPROM
SST28SF040A / SST28VF040A
SST28SF040A / SST28VF040A5.0 & 2.7 4Mb (x8) Byte-Program, Small Erase Sector flash memories
Data Sheet
FEATURES:
* Single Voltage Read and Write Operations - 5.0V-only for SST28SF040A - 2.7-3.6V for SST28VF040A * Superior Reliability - Endurance: 100,000 Cycles (typical) - Greater than 100 years Data Retention * Memory Organization: 512K x8 * Sector-Erase Capability: 256 Bytes per Sector * Low Power Consumption - Active Current: 15 mA (typical) for 5.0V and 10 mA (typical) for 2.7-3.6V - Standby Current: 5 A (typical) * Fast Sector-Erase/Byte-Program Operation - Byte-Program Time: 35 s (typical) - Sector-Erase Time: 2 ms (typical) - Complete Memory Rewrite: 20 sec (typical) * Fast Read Access Time - 5.0V-only operation: 90 and 120 ns - 2.7-3.6V operation: 150 and 200 ns * Latched Address and Data * Hardware and Software Data Protection - 7-Read-Cycle-Sequence Software Data Protection * End-of-Write Detection - Toggle Bit - Data# Polling * TTL I/O Compatibility * JEDEC Standard - Flash EEPROM Pinouts * Packages Available - 32-lead PLCC - 32-lead TSOP (8mm x 14mm and 8mm x 20mm) - 32-pin PDIP
PRODUCT DESCRIPTION
The SST28SF/VF040A are 512K x8 bit CMOS SectorErase, Byte-Program EEPROMs. The SST28SF/VF040A are manufactured using SST's proprietary, high performance CMOS SuperFlash EEPROM Technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternative approaches. The SST28SF/VF040A erase and program with a single power supply. The SST28SF/ VF040A conform to JEDEC standard pinouts for byte wide memories and are compatible with existing industry standard flash EEPROM pinouts. Featuring high performance programming, the SST28SF/ VF040A typically Byte-Program in 35 s. The SST28SF/ VF040A typically Sector-Erase in 2 ms. Both Program and Erase times can be optimized using interface features such as Toggle bit or Data# Polling to indicate the completion of the Write cycle. To protect against an inadvertent write, the SST28SF/VF040A have on chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, the SST28SF/ VF040A are offered with a guaranteed sector endurance of 10,000 cycles. Data retention is rated greater than 100 years. The SST28SF/VF040A are best suited for applications that require reprogrammable nonvolatile mass storage of program, configuration, or data memory. For all system appli(c)2001 Silicon Storage Technology, Inc. S71077-04-000 6/01 310 1
cations, the SST28SF/VF040A significantly improve performance and reliability, while lowering power consumption when compared with floppy diskettes or EPROM approaches. Flash EEPROM technology makes possible convenient and economical updating of codes and control programs on-line. The SST28SF/VF040A improve flexibility, while lowering the cost of program and configuration storage application. The functional block diagram shows the functional blocks of the SST28SF/VF040A. Figures 1, 2, and 3 show the pin assignments for the 32-lead PLCC, 32-lead TSOP and 32, pin PDIP packages. Pin descriptions and operation modes are described in Tables 2 through 5.
Device Operation
Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. Note, during the Software Data Protection sequence the addresses are latched on the rising edge of OE# or CE#, whichever occurs first.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. SSF is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice.
4 Mbit SuperFlash EEPROM SST28SF040A / SST28VF040A
Data Sheet
Command Definitions
Table 4 contains a command list and a brief summary of the commands. The following is a detailed description of the operations initiated by each command.
command can be reissued as many times as necessary to complete the Chip-Erase operation. The SST28SF/ VF040A cannot be over-erased. (See Figure 8)
Byte-Program Operation
The Byte-Program operation is initiated by writing the setup command (10H). Once the program setup is performed, programming is executed by the next WE# pulse. See Figures 5 and 6 for timing waveforms. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first, and begins the Program operation. The Program operation is terminated automatically by an internal timer. See Figure 16 for the programming flowchart. The two-step sequence of a setup command followed by an execute command ensures that only the addressed byte is programmed and other bytes are not inadvertently programmed.
Sector-Erase Operation
The Sector-Erase operation erases all bytes within a sector and is initiated by a setup command and an execute command. A sector contains 256 Bytes. This sector erasability enhances the flexibility and usefulness of the SST28SF/ VF040A, since most applications only need to change a small number of bytes or sectors, not the entire chip. The setup command is performed by writing 20H to the device. The execute command is performed by writing D0H to the device. The Erase operation begins with the rising edge of the WE# or CE#, whichever occurs first and terminates automatically by using an internal timer. The End-ofErase can be determined using either Data# Polling, Toggle Bit, or Successive Reads detection methods. See Figure 9 for timing waveforms. The two-step sequence of a setup command followed by an execute command ensures that only memory contents within the addressed sector are erased and other sectors are not inadvertently erased.
The Byte-Program Flowchart Description
Programming data into the SST28SF/VF040A is accomplished by following the Byte-Program flowchart shown in Figure 16. The Byte-Program command sets up the byte for programming. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first and begins the Program operation. The end of program can be detected using either the Data# Polling, Toggle bit, or Successive reads.
Sector-Erase Flowchart Description
Fast and reliable erasing of the memory contents within a sector is accomplished by following the Sector-Erase flowchart as shown in Figure 18. The entire procedure consists of the execution of two commands. The Sector-Erase operation will terminate after a maximum of 4 ms. A Reset command can be executed to terminate the Sector-Erase operation; however, if the Erase operation is terminated prior to the 4 ms time-out, the sector may not be fully erased. A Sector-Erase command can be reissued as many times as necessary to complete the Erase operation. The SST28SF/VF040A cannot be over-erased.
Reset Operation
The Reset command is provided as a means to safely abort the Erase or Program command sequences. Following either setup commands (Erase or Program) with a write of FFH will safely abort the operation. Memory contents will not be altered. After the Reset command, the device returns to the Read mode. The Reset command does not enable Software Data Protection. See Figure 7 for timing waveforms.
Chip-Erase Operation
The Chip-Erase operation is initiated by a setup command (30H) and an execute command (30H). The Chip-Erase operation allows the entire array of the SST28SF/VF040A to be erased in one operation, as opposed to 2048 SectorErase operations. Using the Chip-Erase operation will minimize the time to rewrite the entire memory array. The ChipErase operation will terminate after a maximum of 20 ms. A Reset command can be executed to terminate the Erase operation; however, if the Chip-Erase operation is terminated prior to the 20 ms time-out, the chip may not be completely erased. If an erase error occurs a Chip-Erase
(c)2001 Silicon Storage Technology, Inc.
Read
The Read operation is initiated by setting CE#, and OE# to logic low and setting WE# to logic high (See Table 3). See Figure 4 for Read cycle timing waveform. The Read operation from the host retrieves data from the array. The device remains enabled for Read until another operation mode is accessed. During initial power-up, the device is in the Read mode and is Software Data protected. The device must be unprotected to execute a Write command.
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4 Mbit SuperFlash EEPROM SST28SF040A / SST28VF040A
Data Sheet The Read operation of the SST28SF/VF040A are controlled by OE# and CE# at logic low. When CE # is high, the chip is deselected and only standby power will be consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when CE# or OE# are high. rising edge of OE# or CE#, whichever occurs first. A similar seven read sequence of 1823H, 1820H, 1822H, 0418H, 041BH, 0419H, 040AH will protect the device. Also refer to Figures 10 and 11 for the 7 read cycle sequence Software Data Protection. The I/O pins can be in any state (i.e., high, low, or tri-state).
Read-ID operation
The Read-ID operation is initiated by writing a single command (90H). A read of address 0000H will output the manufacturer's ID (BFH). A read of address 0001H will output the device ID (04H). Any other valid command will terminate this operation.
Write Operation Status Detection
The SST28SF/VF040A provide three means to detect the completion of a Write operation, in order to optimize the system Write operation. The end of a Write operation (Erase or Program) can be detected by three means: 1) monitoring the Data# Polling bit, 2) monitoring the Toggle bit, or 3) by two successive reads of the same data. These three detection mechanisms are described below. The actual completion of the nonvolatile Write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with the DQ used. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid.
Data Protection
In order to protect the integrity of nonvolatile data storage, the SST28SF/VF040A provide both hardware and software features to prevent inadvertent writes to the device, for example, during system power-up or power-down. Such provisions are described below.
Hardware Data Protection
The SST28SF/VF040A are designed with hardware features to prevent inadvertent writes. This is done in the following ways: 1. Write Cycle Inhibit Mode: OE# low, CE#, or WE# high will inhibit the Write operation. 2. Noise/Glitch Protection: A WE# pulse width of less than 5 ns will not initiate a Write cycle. 3. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 2.0V. 4. After power-up, the device is in the Read mode and the device is in the Software Data Protect state.
Data# Polling (DQ7)
The SST28SF/VF040A feature Data# Polling to indicate the Write operation status. During a Write operation, any attempt to read the last byte loaded during the byte-load cycle will receive the complement of the true data on DQ7. Once the Write cycle is completed, DQ7 will show true data. The device is then ready for the next operation. See Figure 12 for Data# Polling timing waveforms. In order for Data# Polling to function correctly, the byte being polled must be erased prior to programming.
Software Data Protection (SDP)
The SST28SF/VF040A have software methods to further prevent inadvertent writes. In order to perform an Erase or Program operation, a two-step command sequence consisting of a set-up command followed by an execute command avoids inadvertent erasing and programming of the device. The SST28SF/VF040A will default to Software Data Protection after power up. A sequence of seven consecutive reads at specific addresses will unprotect the device The address sequence is 1823H, 1820H, 1822H, 0418H, 041BH, 0419H, 041AH. The address bus is latched on the
(c)2001 Silicon Storage Technology, Inc.
Toggle Bit (DQ6)
An alternative means for determining the Write operation status is by monitoring the Toggle Bit, DQ6. During a Write operation, consecutive attempts to read data from the device will result in DQ6 toggling between logic 0 (low) and logic 1 (high). When the Write cycle is completed, the toggling will stop. The device is then ready for the next operation. See Figure 13 for Toggle Bit timing waveforms.
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Data Sheet
Successive Reads
An Alternative means for determining an end of a write operation is by reading the same address for two consecutive data matches.
SST28SF/VF040A. Users may wish to use the software operation to identify the device (i.e., using the device ID). For details see Table 3 for the hardware operation and Figure 19 for the software operation. The manufacturer and device IDs are the same for both operations. TABLE 1: PRODUCT IDENTIFICATION
Address Manufacturer's ID Device ID SST28SF/VF040A 0001H 04H
T1.1 310
Product Identification
The Product Identification mode identifies the device as SST28SF/VF040A and the manufacturer as SST. This mode may be accessed by hardware and software operations. The hardware operation is typically used by an external programmer to identify the correct algorithm for the
Data BFH
0000H
FUNCTIONAL BLOCK DIAGRAM
X-Decoder
SuperFlash Memory
A18 - A0
Address Buffer & Latches Y-Decoder
CE# OE# WE#
Control Logic
I/O Buffers and Data Latches DQ7 - DQ0
310 ILL B1.1
WE#
VDD
A12
A15
A16
A18
A7 A6 A5 A4 A3 A2 A1 A0 DQ0
5 6 7 8 9 10 11 12 13
4
3
2
1
32 31 30 29 28 27 26 25 24 23 22
A17
A14 A13 A8 A9 A11 OE# A10 CE# DQ7
32-lead PLCC Top View
21 14 15 16 17 18 19 20 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6
310 ILL F02.3
FIGURE 1: PIN ASSIGNMENTS FOR 32-LEAD PLCC
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4 Mbit SuperFlash EEPROM SST28SF040A / SST28VF040A
Data Sheet
A11 A9 A8 A13 A14 A17 WE# VDD A18 A16 A15 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Standard Pinout Top View Die Up
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3
310 ILL F01.2
FIGURE 2: PIN ASSIGNMENTS FOR 32-LEAD TSOP
A18 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
1 2 3 4 5 32-pin 6 PDIP 7 8 Top View 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VDD WE# A17 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3
310 ILL F19.0
FIGURE 3: PIN ASSIGNMENTS FOR 32-PIN PDIP TABLE 2: PIN DESCRIPTION
Symbol A18-A8 A7-A0 Pin Name Row Address Inputs Column Address Inputs Data Input/output Functions To provide memory addresses. Row addresses define a sector. Selects the byte within the sector To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. To activate the device when CE# is low.1 To gate the data output buffers. To control the Write operations.1 To provide: 5.0V supply (10%) for SST28SF040A 2.7V supply (2.7-3.6V) for SST28VF040A
T2.2 310
DQ7-DQ0
CE# OE# WE# VDD VSS
Chip Enable Output Enable Write Enable Power Supply Ground
1. This pin is internally pull-up with a resistor.
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4 Mbit SuperFlash EEPROM SST28SF040A / SST28VF040A
Data Sheet TABLE 3: OPERATION MODES SELECTION
Mode Read Byte-Program Sector-Erase Standby Write Inhibit Software Chip-Erase Product Identification Hardware Mode Software Mode SDP Enable & Disable Mode Reset VIL VIL VIL VIL VIL VIL VIL VIH VIH VIH VIH VIL Manufacturer's ID (BFH) Device ID (04H) A18-A1=VIL, A9=VH, A0=VIL A18-A1=VIL, A9=VH, A0=VIH See Table 4 See Table 4 See Table 4
T3.4 310
CE# VIL VIL VIL VIH X X VIL
OE# VIL VIH VIH X1 VIL X VIH
WE# VIH VIL VIL X X VIH VIL
DQ DOUT DIN DIN High Z High Z/ DOUT High Z/ DOUT DIN
Address AIN AIN, See Table 4 AIN, See Table 4 X X X See Table 4
1. X can be VIL or VIH, but no other value.
TABLE 4: SOFTWARE COMMAND SUMMARY
Required Command Summary Sector-Erase Byte-Program Chip-Erase6 Reset Read-ID Software Data Protect Software Data Unprotect
1. 2. 3. 4. 5.
Setup Command Cycle Type1 W W W W W R R Addr2,3 X X X X X
8 9
Execute Command Cycle Type1 W W W R Addr2,3 SA PA X
7
Cycle(s) 2 2 2 1 2 7 7
Data4 20H 10H 30H FFH 90H
Data4 D0H PD 30H
7
SDP5 N N N Y Y
T4.3 310
6. 7. 8. 9.
Type definition: W = Write, R = Read, X can be VIL or VIH, but no other value. Addr (Address) definition: SA = Sector Address = A18 - A8, sector size = 256 Bytes; A7- A0 = X for this command. Addr (Address) definition: PA = Program Address = A18 - A0. Data definition: PD = Program Data, H = number in hex. SDP = Software Data Protect mode using 7 Read Cycle Sequence. a) Y = the operation can be executed with protection enabled b) N = the operation cannot be executed with protection enabled The Chip-Erase function is not supported on SST28VF040A industrial parts. Address 0000H retrieves the Manufacturer's ID of BFH and address 0001H retrieves the Device ID of 04H. Refer to Figure 11 for the 7 Read Cycle sequence for Software_Data_Protect. Refer to Figure 10 for the 7 Read Cycle sequence for Software_Data_Unprotect.
TABLE 5: MEMORY ARRAY DETAIL
Sector Select A18 - A8 Byte Select A7 - A0
T5.0 310
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4 Mbit SuperFlash EEPROM SST28SF040A / SST28VF040A
Data Sheet Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD + 0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to VDD + 1.0V Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 14.0V Package Power Dissipation Capability (Ta = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Through Hold Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300C Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240C Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE
Range Commercial Industrial
FOR
SST28SF040A
VDD 5.0V10% 5.0V10%
Ambient Temp 0C to +70C -40C to +85C
FOR
OPERATING RANGE
Range Commercial Industrial
SST28VF040A
VDD 2.7-3.6V 2.7-3.6V
Ambient Temp 0C to +70C -40C to +85C
OF
AC CONDITIONS
TEST
Input Rise/Fall Time . . . . . . . . . . . . . . 10 ns Output Load . . . . . . . . . . . . . . . . . . . . . 1 TTL Gate andCL = 100 pF for SST28SF040A CL = 100 pF for SST28VF040A See Figures 14 and 15
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4 Mbit SuperFlash EEPROM SST28SF040A / SST28VF040A
Data Sheet TABLE 6: DC OPERATING CHARACTERISTICS
Symbol IDD Parameter Power Supply Current Read Program and Erase ISB1 ISB2 ILI ILO VIL VIH VOL VOH VH IH Standby VDD Current (TTL input) Standby VDD Current (CMOS input) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Supervoltage for A9 Supervoltage Current for A9 2.4 11.6 12.4 200 2.0 0.4 32 40 3 20 1 10 0.8 mA mA mA A A A V V V V V A
FOR
SST28SF040A
Limits Max Units Test Conditions Address input=VIL/VIH, at f=1/TRC Min, VDD=VDD Max CE#=OE#=VIL, WE#=VIH, all I/Os open CE#=WE#=VIL, OE#=VIH, VDD=VDD Max CE#=VIH, VDD=VDD Max CE#=VDD-0.3V, VDD=VDD Max VIN=GND to VDD, VDD=VDD Max VOUT=GND to VDD, VDD=VDD Max VDD=VDD Min VDD=VDD Max IOL=2.1 mA, VDD=VDD Min IOH=-400 A, VDD=VDD Min CE#=OE#=VIL, WE#=VIH CE#=OE#=VIL, WE#=VIH, A9=VH Max
T6.4 310
Min
TABLE 7: DC OPERATING CHARACTERISTICS
Symbol IDD Parameter Power Supply Current Read Program and Erase ISB2 ILI ILO VIL VIH VOL VOH VH IH Standby VDD Current (CMOS input) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Supervoltage for A9 Supervoltage Current for A9
FOR
SST28VF040A
Limits Max Units Test Conditions Address input=VIL/VIH, at f=1/TRC Min, VDD=VDD Max 10 25 20 1 10 0.8 mA mA A A A V V 0.4 V V 12.4 200 V A CE#=OE#=VIL, WE#=VIH, all I/Os open CE#=WE#=VIL, OE#=VIH, VDD=VDD Max CE#=OE#=WE#=VDD-0.3V, VDD=VDD Max VIN=GND to VDD, VDD=VDD Max VOUT=GND to VDD, VDD=VDD Max VDD=VDD Min VDD=VDD Max IOL=100 A, VDD=VDD Min IOH=-100 A, VDD=VDD Min CE#=OE#=VIL, WE#=VIH CE#=OE#=VIL, WE#=VIH, A9=VH Max
T7.4 310
Min
2.0 2.4 11.6
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4 Mbit SuperFlash EEPROM SST28SF040A / SST28VF040A
Data Sheet TABLE 8: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol TPU-READ1 TPU-WRITE
1
Parameter Power-up to Read Operation Power-up to Write Operation
Minimum 10 10
Units ms ms
T8.4 310
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 9: CAPACITANCE
Parameter CI/O
1
(Ta = 25C, f=1 Mhz, other pins open)
Description I/O Pin Capacitance Input Capacitance
Test Condition VI/O = 0V VIN = 0V
Maximum 12 pF 6 pF
T9.0 310
CIN1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 10: RELIABILITY CHARACTERISTICS
Symbol NEND TDR1 ILTH1
1
Parameter Endurance Data Retention Latch Up
Minimum Specification 10,000 100 100 + IDD
Units Cycles Years mA
Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard 78
T10.7 310
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
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4 Mbit SuperFlash EEPROM SST28SF040A / SST28VF040A
Data Sheet
AC CHARACTERISTICS
TABLE 11: READ CYCLE TIMING PARAMETERS
IEEE Symbol tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tELQX tGLQX tAXQX Industry Symbol TRC TAA TCE TOE TCLZ1 TOLZ
1
FOR
SST28SF040A
SST28SF040A-90 SST28SF040A-120 Min 120 90 90 45 0 0 20 20 0 0 0 0 30 30 120 120 50 Max Units ns ns ns ns ns ns ns ns ns
T11.6 310
Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time CE# Low to Active Output OE# Low to Active Output CE# High to High-Z Output OE# High to High-Z Output Output Hold from Address Change
Min 90
Max
TCHZ1 TOHZ TOH1
1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 12: READ CYCLE TIMING PARAMETERS
IEEE Symbol tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tELQX tGLQX tAXQX Industry Symbol TRC TAA TCE TOE TCLZ1 TOLZ1 TCHZ1 TOHZ1 TOH1 Parameter Read Cycle Time Address Access Time Chip Enable Access Time
FOR
SST28VF040A
SST28VF040A-150 Min 150 150 150 75 0 0 40 40 0 0 0 0 60 60 Max SST28VF040A-200 Min 200 200 200 100 Max Units ns ns ns ns ns ns ns ns ns
T12.5 310
Output Enable Access Time CE# Low to Active Output OE# Low to Active Output CE# High to High-Z Output OE# High to High-Z Output Output Hold from Address Change
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
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4 Mbit SuperFlash EEPROM SST28SF040A / SST28VF040A
Data Sheet TABLE 13: ERASE/PROGRAM CYCLE TIMING PARAMETERS
IEEE Symbol tAVA tWLWH tAVWL tWLAX tELWL tWHEX tGHWL tWGL tWLEH tDVWH tWHDX tWHWL2 tWHWL3 tEHEL tWHWL1 Industry Symbol TBP TWP TAS TAH TCS TCH TOES TOEH TCP TDS TDH TSE TRST1 TSCE TCPH TWPH TPCP1 TPCH1 TPAS1 TPAH1 SST28SF040A Parameter Byte-Program Cycle Time Write Pulse Width (WE#) Address Setup Time Address Hold Time CE# Setup Time CE# Hold Time OE# High Setup Time OE# High Hold Time Write Pulse Width (CE#) Data Setup Time Data Hold Time Sector-Erase Cycle Time Reset Command Recovery Time Software Chip-Erase Cycle Time CE# High Pulse Width WE# High Pulse Width Protect CE# or OE# Pulse Width Protect CE# or OE# High Time Protect Address Setup Time Protect Address Hold Time 50 50 50 50 40 0 90 10 50 0 0 10 10 90 50 10 4 4 20 50 50 50 50 40 0 Min Max 40 100 10 100 0 0 20 20 100 100 20 4 4 20 SST28VF040A Min Max 40 Units s ns ns ns ns ns ns ns ns ns ns ms s ms ns ns ns ns ns ns
T13.6 310
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
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4 Mbit SuperFlash EEPROM SST28SF040A / SST28VF040A
Data Sheet
TRC ADDRESS A18-0 TCE CE# TOE OE#
TAA
TCHZ
TOHZ
TOLZ WE# TCLZ DQ 7-0 TOH DATA VALID DATA VALID
310 ILL F03.2
FIGURE 4: READ CYCLE TIMING DIAGRAM
TAS ADDRESS A18-0
TAH
TCS CE# TOES OE# TWP WE# TDH DQ 7-0 I0H TDS
BYTE-PROGRAM SETUP COMMAND
TCH
TOEH
TWPH
TDS DATA VALID TDH TBP
310 ILL F04.1
FIGURE 5: WE# CONTROLLED BYTE-PROGRAM CYCLE TIMING DIAGRAM
(c)2001 Silicon Storage Technology, Inc.
S71077-04-000 6/01
310
12
4 Mbit SuperFlash EEPROM SST28SF040A / SST28VF040A
Data Sheet
TAS ADDRESS A18-0 TCPH CE#
TAH
TCP TOEH TOES
OE# TCH WE# TDH DQ 7-0 I0H TDS
BYTE-PROGRAM SETUP COMMAND
TCS TDS DATA VALID TDH TBP
310 ILL F05.1
FIGURE 6: CE# CONTROLLED BYTE-PROGRAM CYCLE TIMING DIAGRAM
ADDRESS A18-0
CE#
OE#
WE# TDS DQ 7-0 FFH TDH TRST
310 ILL F06.0
FIGURE 7: RESET COMMAND TIMING DIAGRAM
(c)2001 Silicon Storage Technology, Inc.
S71077-04-000 6/01
310
13
4 Mbit SuperFlash EEPROM SST28SF040A / SST28VF040A
Data Sheet
ADDRESS A18-0
CE#
OE#
WE# TDH TDS DQ 7-0 30H TDS 30H TSCE SETUP COMMAND EXECUTE COMMAND
310 ILL F07.0
TDH
FIGURE 8: CHIP-ERASE TIMING DIAGRAM
ADDRESS A18-0 TAS CE#
AIN
TAH
OE#
WE# TDH TDS DQ 7-0 20H TDS D0H TSE SETUP COMMAND EXECUTE COMMAND
310 ILL F08.0
TDH
FIGURE 9: SECTOR-ERASE TIMING DIAGRAM
(c)2001 Silicon Storage Technology, Inc.
S71077-04-000 6/01
310
14
4 Mbit SuperFlash EEPROM SST28SF040A / SST28VF040A
Data Sheet
OE# TPCP CE# TPCH
WE#
ADDRESS TPAS
1823
1820 TPAH
1822
0418
041B
0419
041A
NOTE: A. ADDRESSES ARE LATCHED INTERNALLY ON THE RISING EDGE OF: 1. OE# IF CE# IS KEPT AT LOW ALL TIME. 2. CE# IF OE# IS KEPT AT LOW ALL TIME. 3. THE FIRST PIN TO GO HIGH IF BOTH ARE TOGGLED. B. ABOVE ADDRESS VALUES ARE IN HEX. C. ADDRESSES > A12 ARE "DON'T CARE"
310 ILL F09.4
FIGURE 10: SOFTWARE DATA UNPROTECT DISABLE TIMING DIAGRAM
OE# TPCP CE# TPCH
WE#
ADDRESS TPAS
1823
1820 TPAH
1822
0418
041B
0419
040A
NOTE: A. ADDRESSES ARE LATCHED INTERNALLY ON THE RISING EDGE OF: 1. OE# IF CE# IS KEPT AT LOW ALL TIME. 2. CE# IF OE# IS KEPT AT LOW ALL TIME. 3. THE FIRST PIN TO GO HIGH IF BOTH ARE TOGGLED. B. ABOVE ADDRESS VALUES ARE IN HEX. C. ADDRESSES > A12 ARE "DON'T CARE"
310 ILL F10.4
FIGURE 11: SOFTWARE DATA PROTECT DISABLE TIMING DIAGRAM
(c)2001 Silicon Storage Technology, Inc.
S71077-04-000 6/01
310
15
4 Mbit SuperFlash EEPROM SST28SF040A / SST28VF040A
Data Sheet
ADDRESS A18-0 TCE CE# TOEH OE# TOE WE# D DQ 7-0 NOTE
310 ILL F11.0
TOES
D#
D#
D
NOTE: THIS TIME INTERVAL SIGNAL CAN BE TSE or TBP DEPENDING UPON THE SELECTED OPERATION MODE.
FIGURE 12: DATA# POLLING TIMING DIAGRAM
ADDRESS A18-0 TCE CE# TOEH OE# TOE TOE WE# TOES TCE
DQ6 NOTE
TWO READ CYCLES WITH SAME OUTPUTS
310 ILL F12.0
NOTE: THIS TIME INTERVAL SIGNAL CAN BE TSE or TBP DEPENDING UPON THE SELECTED OPERATION MODE.
FIGURE 13: TOGGLE BIT TIMING DIAGRAM
(c)2001 Silicon Storage Technology, Inc.
S71077-04-000 6/01
310
16
4 Mbit SuperFlash EEPROM SST28SF040A / SST28VF040A
Data Sheet
VIHT VHT
INPUT REFERENCE POINTS
VHT
OUTPUT
VLT VILT
VLT
310 ILL F13.1
AC test inputs are driven at VIHT (2.4V) for a logic "1" and VILT (0.4 V) for a logic "0". Measurement reference points for inputs and outputs are VHT (2.0 V) and VLT (0.8 V). Input rise and fall times (10% 90%) are <10 ns.
Note: VHT - VHIGH Test VLT - VLOW Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test
FIGURE 14: AC INPUT/OUTPUT REFERENCE WAVEFORMS
TEST LOAD EXAMPLE VDD TO TESTER RL HIGH
TO DUT CL RL LOW
310 ILL F14.2
FIGURE 15: A TEST LOAD EXAMPLE
(c)2001 Silicon Storage Technology, Inc.
S71077-04-000 6/01
310
17
4 Mbit SuperFlash EEPROM SST28SF040A / SST28VF040A
Data Sheet
Start
Initialize Address
Execute ByteProgram Setup Command
Load Address and Data & Start Programming
Read End-of-Write Detection
Programming Completed?
No
Yes Data Verifies? Yes No Last Address Yes Programming Completed
310 ILL F15.3
Next Address
No
Programming Failure
FIGURE 16: BYTE-PROGRAM FLOWCHART
(c)2001 Silicon Storage Technology, Inc.
S71077-04-000 6/01
310
18
4 Mbit SuperFlash EEPROM SST28SF040A / SST28VF040A
Data Sheet
Internal Timer
Program/Erase Initiated
Toggle Bit
Program/Erase Initiated
Data# Polling
Program/Erase Initiated
Wait TBP or TSE
Read byte
Read DQ7
Program/Erase Completed
Read same byte
No
Is DQ7 = true data?
Yes No Program/Erase Completed
Does DQ6 match?
Yes Program/Erase Completed
310 ILL F16.2
FIGURE 17: WRITE WAIT OPTIONS
(c)2001 Silicon Storage Technology, Inc.
S71077-04-000 6/01
310
19
4 Mbit SuperFlash EEPROM SST28SF040A / SST28VF040A
Data Sheet
Start
Initialize Sector Address
Execute Two Step Sector-Erase Command
End-of-Write Detection
Erase completed?
No
Yes Read FFH from Selected Byte Address
Verify FFH
No
Yes Increment Byte Address No
Last Address?
Yes Next Sector Address Sector-Erase Completed Erase Error
No
Last Sector?
Yes Device Erased
310 ILL F17.5
FIGURE 18: SECTOR-ERASE FLOWCHARTS
(c)2001 Silicon Storage Technology, Inc. S71077-04-000 6/01 310
20
4 Mbit SuperFlash EEPROM SST28SF040A / SST28VF040A
Data Sheet
Execute Read ID Command (90H) to Enter Read-ID mode
Read Address 0000H MFG's ID = SST (BFH)
Read Address 0001H Device ID = 28SF040 (04H)
Execute Reset Command (FFH) to Exit from Read-ID mode
310 ILL F18.5
FIGURE 19: SOFTWARE PRODUCT ID FLOW
(c)2001 Silicon Storage Technology, Inc.
S71077-04-000 6/01
310
21
4 Mbit SuperFlash EEPROM SST28SF040A / SST28VF040A
Data Sheet
PRODUCT ORDERING INFORMATION
Device Speed Suffix1 XX Suffix2 XX Package Modifier H = 32 leads or pins Package Type N = PLCC W = TSOP (die up) (8mm x 14mm) E = TSOP (die up) (8mm x 20mm) P = PDIP Temperature Range C = Commercial = 0C to +70C I = Industrial = -40C to +85C Minimum Endurance 4 = 10,000 cycles Read Access Speed 200 = 200 ns 150 = 150 ns 120 = 120 ns 90 = 90 ns Voltage S = 4.5-5.5V V = 2.7-3.6V
SST28xF040A - XXX
Valid combinations for SST28SF040A SST28SF040A-90-4C-NH SST28SF040A-90-4C-WH SST28SF040A-90-4C-EH SST28SF040A-90-4C-PH SST28SF040A-120-4C-NH SST28SF040A-120-4C-WH SST28SF040A-120-4C-EH SST28SF040A-120-4I-NH SST28SF040A-120-4I-WH SST28SF040A-120-4I-EH
Valid combinations for SST28VF040A SST28VF040A-150-4C-NH SST28VF040A-150-4C-WH SST28VF040A-150-4C-EH SST28VF040A-200-4C-NH SST28VF040A-200-4C-WH SST28VF040A-200-4C-EH SST28VF040A-200-4I-NH
Note: Note:
SST28VF040A-200-4I-WH
SST28VF040A-200-4I-EH
Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. The software Chip-Erase function is not supported by the industrial temperature part. Please contact SST, if you require this function for an industrial temperature part.
(c)2001 Silicon Storage Technology, Inc.
S71077-04-000 6/01
310
22
4 Mbit SuperFlash EEPROM SST28SF040A / SST28VF040A
Data Sheet
PACKAGING DIAGRAMS
TOP VIEW
.485 .495 .447 .453 .042 .048
2 1 32
SIDE VIEW
.106 .112 .020 R. MAX. .023 x 30 .029 .030 R. .040
BOTTOM VIEW
Optional Pin #1 Identifier
.042 .048 .585 .595 .547 .553 .026 .032
.013 .021 .400 BSC
.490 .530
.050 BSC. .015 Min. .050 BSC. .125 .140 .075 .095 .026 .032
Note:
1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches. 32.PLCC.NH-ILL.2 4. Coplanarity: 4 mils.
32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC) SST PACKAGE CODE: NH
Pin # 1 Identifier
1.05 0.95 .50 BSC
8.10 7.90
.270 .170
12.50 12.30
0.15 0.05
0.70 0.50
14.20 13.80
32.TSOP-WH-ILL.4
Note:
1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (.05) mm. 4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads.
32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM SST PACKAGE CODE: WH
X
14MM
(c)2001 Silicon Storage Technology, Inc.
S71077-04-000 6/01
310
23
4 Mbit SuperFlash EEPROM SST28SF040A / SST28VF040A
Data Sheet
1.05 0.95 .50 BSC
Pin # 1 Identifier
8.10 7.90
.27 .17
18.50 18.30
0.15 0.05
0.70 0.50
20.20 19.80
32.TSOP-EH-ILL.4
Note:
1. Complies with JEDEC publication 95 MO-142 BD dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (.05) mm. 4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads.
32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM SST PACKAGE CODE: EH
X
20MM
32
C L
.600 .625
Pin #1 Identifier
.065 .075
1
1.645 1.655 7 4 PLCS.
.530 .550
Base Plane Seating Plane
.015 .050 .120 .150
.170 .200
.008 .012 .600 BSC
0 15
.070 .080
.045 .065
.016 .022
.100 BSC
Note:
1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches.
32.pdipPH-ILL.2
32-PIN PLASTIC DUAL-IN-LINE PACKAGE (PDIP) SST PACKAGE CODE: PH
Silicon Storage Technology, Inc. * 1171 Sonora Court * Sunnyvale, CA 94086 * Telephone 408-735-9110 * Fax 408-735-9036 www.SuperFlash.com or www.ssti.com
(c)2001 Silicon Storage Technology, Inc. S71077-04-000 6/01 310
24

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